statistical device modeling useful in technology optimization;
some methodologies for the statistical design flow of Integrated Circuits subject to statistical technological tolerances with particular attention to device mismatch.
The main qualifying points of this research are:
Experimental CMOS process characterization and statistical modeling.
Statistical circuits simulations and yield optimization for IC statistical design.
Implementation of the tool SiSMA for statistical simulation of MOS ICs using a non-Montecarlo approach.
